This invention relates in general to electronic devices, and more particularly to a system and method for processing a transistor channel layout.
A photomask is generally used to establish a pattern for the fabrication of a transistor channel. The photomask is generated according to a transistor channel layout. Transistor channel layouts often include bends between a first end of the channel and a second end of the channel in order to increase the packing density of transistors on an integrated circuit board. A drawback to patterning bends in a transistor channel layout is that upon fabrication of the transistor, the length of the transistor channel may be non-uniform over the width of the channel from the first end to the second end. These non-uniformities in transistor channel dimensions degrade the transistor performance.
In accordance with the present invention, a system for processing a transistor channel layout is provided which substantially eliminates or reduces disadvantages and problems associated with previous systems.
In accordance with one embodiment of the present invention, a system for processing a transistor channel layout includes a memory and a processor. The memory stores input layout data defining a transistor channel layout having a bend between a first end and a second end. The memory further stores contour adjustment data. The processor adjusts the bend of the transistor channel layout according to the contour adjustment data and generates output layout data defining the adjusted transistor channel layout.
Another embodiment of the present invention is a method for processing a transistor channel layout, wherein the method includes receiving input layout data defining a transistor channel layout having a bend between a first end and a second end. The method continues by receiving contour adjustment data and adjusting the bend of the transistor channel layout according to the contour adjustment data. The method concludes by generating output layout data defining the adjusted transistor channel layout.
Yet another embodiment of the present invention is a transistor channel layout defined by layout data. The layout includes a bend between a first end and a second end. The bend includes an inner corner and an outer corner wherein a portion of the outer corner is removed to form a corner edge at a particular angle.
A technical advantage of the present invention is a technique for processing transistor channel layouts. An adjusted transistor channel layout of the present invention may be used to fabricate a transistor channel that meets particular dimension and/or performance parameters. For example, an advantage to fabricating a transistor channel using an adjusted transistor channel layout is that the length of the channel is uniform over the width of the transistor channel from a first end of the channel to the second end of the channel. This results in a high transistor packing density while maintaining transistor performance and speed.
Other technical advantages are readily apparent to one of skill in the art from the attached figures, description, and claims.